1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor device including a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device which can be effectively fabricated using multi chip module (hereinafter, simply referred to as an "MCM") technologies and a semiconductor device including such a semiconductor memory device.
2. Description of the Related Art
A dynamic random access memory (DRAM) device is a widely used semiconductor memory device. A DRAM generally includes a memory cell array including a plurality of memory cells arranged in an array as a memory section. In order to reduce the number of pins used for a package of a DRAM, a chip having a circuit configuration shown in FIG. 1 is generally formed. As shown in FIG. 1, the DRAM 95 includes a circuit block 50 where a memory cell array 1 including a plurality of memory cells arranged in an array is provided as a center section, and the following circuits are laid out at the same pitch as the pitch for the plurality of memory cells inside the memory cell array 1: a row decoder 5 and a word driver 6 for selecting a word line; a sense amplifier 4 for amplifying a signal on a bit line; a column selector 3 for selecting a bit data at an arbitrary position from the signal amplified by the sense amplifier 4 so as to output the selected data to a data line; and a column decoder 2 for generating a select signal to be supplied to the column selector 3. Hereinafter, such a circuit block 50 including the memory cell array 1 and the above circuits laid out at the same pitch as the pitch for the plurality of memory cells inside the memory cell array 1 will be called a "memory core section". Furthermore, the following circuits are laid out without depending upon the memory cell pitch inside the memory cell array 1: a row address buffer 10 for receiving a row address from an address signal A(10:0) input terminal 32; a column address buffer 9 for receiving a column address through the same terminal 32; a row address counter 11 for generating a refresh address; a row pre-decoder 8 for decoding an input address signal beforehand so as to convert the signal output from the row address buffer 10 into a signal applied to the row decoder 5; a column pre-decoder 7 for decoding an input address signal beforehand so as to convert the signal output from the column address buffer 9 into a signal applied to the column decoder 2; a data input buffer 12 for inputting a data to a data DQ(7:0) input terminal 36; a data output buffer 13 for outputting a data from the data DQ(7:0) output terminal 36; a write amplifier 14 for writing a data onto a memory cell; a read amplifier 15 for reading out a data from a memory cell; an RAS/CAS-clock generator 16 for generating a timing signal used inside the DRAM based on an RAS signal and a CAS signal input through an RAS signal input terminal 30 and a CAS signal input terminal 31, respectively; a WE-clock generator 17 for generating a write timing signal based on a WE signal input through a WE signal input terminal 35; an OE-clock generator 18 for generating a timing signal for an output data based on an OE signal input through an OE signal input terminal 37; a boosting potential generator 19 for generating a voltage required for the inside of the DRAM so as to boost a word line potential; a substrate potential generator 20 for generating a potential applied to a substrate; and a 1/2 VCC generator 21 for generating a 1/2 VCC required as a potential applied to a bit line pre-charge and a cell plate. Hereinafter, the above circuits laid out without depending upon the memory cell pitch inside the memory cell array 1 will be called a "memory peripheral circuit section" as a whole.
Since the DRAM 95 includes on one chip the above-described circuits shown in FIG. 1, only address pins, data pins, several control signal pins and power supply pins are necessary as external pins for mounting the DRAM on a package. Therefore, the DRAM can be mounted on a small package. For example, in an eight bit data I/O 16 Mbit DRAM, 11 address pins, 8 data input/output pins, 4 control signal pins and 2 power supply pins, i.e., 25 pins in total, are used. Accordingly, such a DRAM can be mounted on a package with 28 pins.
FIG. 2 shows an exemplary layout for the DRAM (16 Mbit DRAM in this case) having the circuit configuration shown in FIG. 1. As shown in FIG. 2, the memory cell array 1 is divided into four 4 Mbit plates, and each 4 Mbit plate is further divided into sixteen 256 Kbit memory cell blocks. Each 256 Kbit memory cell block 96 includes memory cells in 256 rows.times.1024 columns. The number of sense amplifiers 4 and column selectors 3 provided for each memory cell block is the same as the number of the columns of the memory cell, i.e., 1024. The row decoder 5 and the word driver 6 are provided for each memory cell block; the column decoder 2 is provided for each plate; and the memory peripheral circuit section is disposed in the portion 94 between the right and left side column decoders 2 in the center portion of the chip and in the peripheral portion of the chip. In this case, the select signal output from the column decoder 2 to the column selector 3 is a signal commonly used for the plates on right and left sides. Because the select signal line cannot cross the memory peripheral circuit section 94 in the center portion, the column decoders 2 are disposed on right and left plates respectively. Pads used for connecting the chip with external pins are disposed in pad formation sections 40 in the center portion 94 of the chip. These pads and the external pins of the package are connected with a wire bond.
In this case, the terminal capacitance of the data input/output terminal 36 for inputting/outputting the data becomes the largest among the terminal capacitances of the respective signal terminals 30 to 32 and 35 to 37 when the chip is mounted on the package. A total terminal capacitance, obtained by adding the gate capacitance of an input transistor; a line capacitance from the terminals to the input transistor; a capacitance of a device for protecting the input transistor from an electric surge; a diffusion capacitance of a signal output transistor; a capacitance of a device for protecting the output transistor from an electric surge; and capacitances of a lead and a wire bond of the package, approximately 5 pF. A plurality of memory devices are generally provided for a system, and the respective terminals of the plurality of memory devices are commonly connected with each other via bus lines. Accordingly, the characteristics of a DRAM are generally estimated assuming that a load capacitance of 50 pF is connected with the respective pins. Currently, a data I/O with a bit width of about 8 to 16 bits is practically used in consideration of not only the limitation of the number of the package pins but also the increase in the power consumption and the noise caused by the load capacitance drive.
FIG. 3 shows an embodiment of a system using a DRAM. In FIG. 3, a packaged DRAM 72 and signal processing LSI 71 such as a CPU are soldered together with a printed wiring board 70. The DRAM 72 and the signal processing LSI 71 are connected with each other via a printed wiring 73. FIG. 3 shows a configuration of a system using one DRAM. However, a large number of systems use a plurality of DRAMs.
A DRAM is fabricated by performing complicated semiconductor fabrication processes having a large number of process steps in order to fabricate a small-area and large-capacity memory cell capacitor or a memory cell transistor with a small amount of leakage current. Accordingly, the fabrication cost of the DRAM using a 0.5 .mu.m design rule is about 1.5 times as high as the fabrication cost of a logic LSI fabrication process for forming a logic LSI using the same design rule.
In the DRAM having the circuit configuration shown in FIG. 1, the DRAM fabrication process is necessary only for the memory cell array 1, and the components other than the memory cell array 1 on the chip can be fabricated using the logic LSI process for forming a logic LSI. However, as shown in FIG. 2, all the components of the DRAM having the circuit configuration shown in FIG. 1 are fabricated using the DRAM fabrication process, so that the fabrication cost of the DRAM becomes disadvantageously high.
This is true of semiconductor memory devices other than the DRAM. In an SRAM, an EEPROM, a flash memory and the like, the portion including the peripheral circuit section other than the memory cell array is formed on one chip using processes requiring a higher cost as compared with a logic LSI fabrication process, thereby further increasing the cost of the semiconductor memory device.
In addition, as described above, the bit width of the data I/O generally used for a memory device is as small as 8 to 16 bits. Therefore, in a system for transmitting a data with a large bit width, the data I/O with a large bit width is formed using a large number of memory devices with a small capacity. As a result, such a system becomes large scale and requires a higher cost.
On the other hand, as a small-sized and faster response system has been developed, MCM technologies for mounting a plurality of bare chips including memory devices on one and the same substrate and connecting the chips with a shortest wiring has been developed. However, in the memory chip used for such an MCM, the expensive memory devices fabricated in a conventional configuration shown in FIG. 2 are used, and the bit width of the data I/O on one memory chip is limited. Therefore, in order to realize a large bit width data I/O, it is necessary to use a large number of memory devices with a small capacity.
Furthermore, in order to improve the data storage characteristics of the memory cells and accelerate the access time, the potential of the semiconductor substrate of a DRAM is set to be negative. This negative potential is generated by a substrate potential generator 20 integrated on the DRAM chip. On the other hand, the semiconductor substrate used for a logic LSI is generally grounded. Therefore, the impedance of the semiconductor substrate for the DRAM becomes higher than the impedance of the semiconductor substrate for the logic LSI, so that the latch up and the electric surge resistance of the DRAM are degraded. As a result, a large area section for protecting the input from an electric surge is required, and a triple well structure process where only the memory cell region on the substrate is set to be at a negative potential is required for a DRAM fabricated by a fine patterning process, thereby further increasing the cost of the DRAM.
Moreover, in a system using memory devices, plural kinds of memory devices, not only the DRAM but also an SRAM, an EEPROM, a flash memory and the like, are frequently used. In all these memory devices, the peripheral circuits are mounted on one and the same chip where the memory cells are mounted, so that every memory chip includes the circuits operating in the same manner.